As part of the general trend of towards smaller and cheaper interconnect technologies microbump copper pillars are attracting attention in the microelectronic industry for the design of advanced semiconductor circuits with high interconnection densities. Copper pillars show good advantages of better electrical properties and higher stand-off height for underfill processes and smaller bump pitches and hence a higher number of IO counts can be achieved. Several publications about copper pillars with bump pitches in the range of 10 μm till 30 μm can be found, and “Sacrificial ion beam etching process for seed layer removal of 6 μm pitch CuSn micro bumps”, by J. Hess et al., IOP Conf. Series: Materials Science and Engineering 41 (2012) 012005, describes the fabrication process of copper pillars with a bump pitch of 6 μm using an ion beam etching (IBE) process for removing the TiW/Cu seed layer without any undercut.
Further, “Microbumping technology for Hybrid IR detectors, 10 μm pitch and beyond”, by B. Majeed et al., Electronics Packaging Technology Conference (EPTC), 2014 IEEE 16th, pp 453-457, 3-5 Dec. 2014, shows the feasibility of microbump fabrication processes down to 10 μm and beyond. The micro bumps are based on Cu/Ni/Sn semi additive plating and built at wafer level using a process fully compatible with standard packaging infrastructures. Different test materials with 15, 10 and even 5 μm pitch Sn microbumps were processed.